
UM10310 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved.
User manual Rev. 2 — 1 November 2010 78 of 139
NXP Semiconductors
UM10310
P89LPC9321 User manual
Fig 37. I
2
C serial interface block diagram.
INTERNAL BUS
002aaa899
ADDRESS REGISTER
COMPARATOR
SHIFT REGISTER
8
I2ADR
ACK
BIT COUNTER /
ARBITRATION &
SYNC LOGIC
8
I2DAT
TIMING
AND
CONTROL
LOGIC
SERIAL CLOCK
GENERATOR
CCLK
interrupt
INPUT
FILTER
OUTPUT
STAGE
INPUT
FILTER
OUTPUT
STAGE
P1.3
P1.3/SDA
P1.2/SCL
P1.2
timer 1
overflow
CONTROL REGISTERS &
SCL DUTY CYCLE REGISTERS
I2CON
I2SCLH
I2SCLL
8
STATUS
DECODER
status bus
STATUS REGISTER
8
I2STAT
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