Nxp-semiconductors PCA9665 Manual do Utilizador descarregar pdf (Página 13)

Product data sheet Rev. 02 — 7 December 2006 13 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

7.3.2.3 The Clock Rate registers, I2CSCLL and I2CSCLH (indirect addresses 02h and 03h)

I2CSCLL and I2CSCLH are 8-bit read/write registers. They deﬁne the data rate for the

PCA9665 when used as a bus master. The actual frequency is determined by t

HIGH

(time

where SCL is HIGH), t

LOW

(time where SCL is LOW), t

(rise time), and t

(fall time) values.

HIGH

and t

LOW

are calculated based on the values that are programmed into I2CSCLH

and I2CSCLL registers and the internal oscillator frequency. t

and t

are

system/application dependent.

with T

osc

= internal oscillator period = 35 ns ± 5ns

Remark: The I2CMODE register needs to be programmed before programming the

I2CSCLL and I2CSCLH registers in order to know which I

C-bus mode is selected. See

Section 7.3.2.6 “The I

C-bus mode register, I2CMODE (indirect address 06h)” for more

detail.

Standard-mode is the default selected mode at power-up or after reset.

Table 17. I2CSCLL - Clock Rate Low register (indirect address 02h) bit allocation

7 6 5 4 3 2 1 0

L7 L6 L5 L4 L3 L2 L1 L0

Table 18. I2CSCLL - Clock Rate Low register (indirect address 02h) bit description

Bit Symbol Description

7:0 L[7:0] Eight bits deﬁning the LOW state of SCL.

Table 19. I2CSCLH - Clock Rate High register (indirect address 03h) bit allocation

7 6 5 4 3 2 1 0

H7 H6 H5 H4 H3 H2 H1 H0

Table 20. I2CSCLH - Clock Rate High register (indirect address 03h) bit description

Bit Symbol Description

7:0 H[7:0] Eight bits deﬁning the HIGH state of SCL.

SCL

osc

I2CSCLL I2CSCLH+()t

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1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 90 91

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