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Product data sheet Rev. 02 — 7 December 2006 72 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

[1] Parameters are valid over speciﬁed temperature and voltage range.

[2] All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0 V and 3.0 V with a transition time of

5 ns maximum. All time measurements are referenced at input voltages of 1.5 V and output voltages shown in Figure 38 and Figure 40.

[3] Test conditions for outputs: C

= 50 pF; R

= 500 Ω, except open-drain outputs.

Test conditions for open-drain outputs: C

= 50 pF; R

=1kΩ pull-up to V

[4] Initialization time for the serial interface after ENSIO bit goes HIGH in a write operation to the control register.

[5] Resetting the device while actively communicating on the bus may cause glitches or an errant STOP condition.

[6] Upon reset, the full delay will be the sum of t

rst

and the RC time constant of the SDA and SCL bus.

Table 50. Dynamic characteristics (2.5 volt)

[1][2][3]

= 2.5 V

0.2 V; T

amb

−

C to +85

C; unless otherwise speciﬁed. (See Table 49 on page 71 for 3.3 V)

Symbol Parameter Conditions Min Typ Max Unit

Initialization timing

init(po)

power-on initialization time - - 550 µs

Serial interface initialization timing

init(sintf)

serial interface initialization time

[4]

from ENSIO bit HIGH - - 550 µs

RESET timing (see Figure 36)

w(rst)

reset pulse width 10 - - ns

rst

reset time

[5][6]

250 - - ns

rec(rst)

reset recovery time 0 - - ns

INT timing (see Figure 37)

as(int)

interrupt assert time - - 550 ns

das(int)

interrupt de-assert time - - 20 ns

Bus timing (see

Figure 38 and Figure 40)

su(A)

address setup time to RD, WR LOW 0 - - ns

h(A)

address hold time from RD, WR LOW 13 - - ns

su(CE_N)

CE setup time to RD, WR LOW 0 - - ns

h(CE_N)

CE hold time from RD, WR LOW 0 - - ns

w(RDL)

RD LOW pulse width 20 - - ns

w(WRL)

WR LOW pulse width 20 - - ns

d(DV)

data valid delay time after RD and CE LOW - - 22 ns

d(QZ)

data output ﬂoat delay time after RD or CE HIGH - - 17 ns

su(Q)

data output setup time before WR or CE HIGH (write cycle) 12 - - ns

h(Q)

data output hold time after WR HIGH 0 - - ns

w(RDH)

RD HIGH pulse width 18 - - ns

w(WRH)

WR HIGH pulse width 18 - - ns

1 2 ... 67 68 69 70 71 72 73 74 75 76 77 ... 90 91

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