Nxp-semiconductors PCA9665 Manual do Utilizador descarregar pdf (Página 5)

Product data sheet Rev. 02 — 7 December 2006 5 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

6.2 Pin description

[1] HVQFN package die supply ground is connected to both the V

pin and the exposed center pad. The V

pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and

board-level performance, the exposed pad needs to be soldered to the board using a corresponding

thermal pad on the board, and for proper heat conduction through the board thermal vias need to be

incorporated in the PCB in the thermal pad region.

Table 2. Pin description

Symbol Pin Type Description

DIP20,

SO20,

TSSOP20

HVQFN20

D0 1 18 I/O Data bus: Bidirectional 3-state data bus used to

transfer commands, data and status between the bus

controller and the CPU. D0 is the least signiﬁcant bit.

D1 2 19 I/O

D2 3 20 I/O

D3 4 1 I/O

D4 5 2 I/O

D5 6 3 I/O

D6 7 4 I/O

D7 8 5 I/O

i.c. 9 6 - internally connected: must be left ﬂoating (pulled

LOW internally)

10 7

[1]

power Supply ground

WR 11 8 I Write strobe: When LOW and CE is also LOW, the

content of the data bus is loaded into the addressed

WR or CE.

RD 12 9 I Read strobe: When LOW and CE is also LOW,

causes the contents of the addressed register to be

presented on the data bus. The read cycle begins on

the falling edge of

RD.

CE 13 10 I Chip Enable: Active LOW input signal. When LOW,

data transfers between the CPU and the bus

controller are enabled on D0 to D7 as controlled by

the

WR, RD and A0 to A1 inputs. When HIGH,

places the D0 to D7 lines in the 3-state condition.

Data are written into the addressed register on rising

edge of either CE or WR.

A0 14 11 I Address inputs: Selects the bus controller’s internal

registers and ports for read/write operations.

A1 15 12 I

INT 16 13 O Interrupt request: Active LOW, open-drain, output.

This pin requires a pull-up device.

RESET 17 14 I Reset: Active LOW input. A LOW level clears internal

registers and resets the I

C-bus state machine.

SCL 18 15 I/O I

C-bus serial clock input/output (open-drain).

This pin requires a pull-up device.

SDA 19 16 I/O I

C-bus serial data input/output (open-drain). This pin

requires a pull-up device.

20 17 power Power supply: 2.3 V to 3.6 V

1 2 3 4 5 6 7 8 9 10 ... 90 91

Comentários a estes Manuais

Sem comentários

Nxp-semiconductors PCA9665 Manual do Utilizador Página 5

Comentários a estes Manuais

Manuais e produtos relacionados com Hardware Nxp-semiconductors PCA9665