Nxp-semiconductors PCA9665 Manual do Utilizador descarregar pdf (Página 77)

Product data sheet Rev. 02 — 7 December 2006 77 of 91

NXP Semiconductors

PCA9665

Fm+ parallel bus to I

C-bus controller

Fig 41. Deﬁnition of timing on the I

C-bus

SDA

SCL

002aab271

P S

HD;STA

LOW

SU;DAT

HD;DAT

HIGH

SU;STA

HD;STA

SU;STO

BUF

Rise and fall times refer to V

and V

Fig 42. I

C-bus timing diagram

SCL

SDA

HD;STA

SU;DAT

HD;DAT

BUF

SU;STA

LOW

HIGH

VD;ACK

002aac696

protocol

START

condition

(S)

bit 7

MSB

bit 6 bit n bit 0

acknowledge

(A)

SCL

VD;DAT

SU;STO

STOP

condition

(P)

1 2 ... 72 73 74 75 76 77 78 79 80 81 82 ... 90 91

1. General description 1
2. Features 1
3. Applications 2
4. Ordering information 2
5. Block diagram 3
6. Pinning information 4
6.2 Pin description 5
7. Functional description 6
Fm+ parallel bus to I 10
C-bus controller 10
NXP Semiconductors 11
8. PCA9665 modes 16
8.3 Byte mode 17
8.4 Buffered mode 31
8.5 Buffered mode examples 48
8.6 I2CCOUNT register 51
8.7 Acknowledge management (I 53
Buffered modes 53
…continued 56
8.8 Miscellaneous states 57
8.9 Some special cases 58
8.10 Power-on reset 60
002aab966 61
002aab031 61
9. Characteristics of the I 65
9.3 Acknowledge 66
10.1 Speciﬁc applications 67
10.2 Add I 67
C-bus port 67
10.3 Add additional I 68
C-bus ports 68
C-bus serial data stream 68
11. Limiting values 69
12. Static characteristics 70
13. Dynamic characteristics 71
14. Test information 78
15. Package outline 79
16. Handling information 83
17. Soldering 83
18. Abbreviations 87
19. Revision history 87
20. Legal information 89
21. Contact information 89
22. Contents 90

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